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sequential logic & flip-flops

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4 detailed 50-minute lessons with teaching scripts, worked examples, parent guides, and assessment criteria.

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Lesson Overview

Total Lessons: 4
Tier: Foundation and Higher
Duration: 50 minutes per lesson (200 minutes total)
Exam Boards: AQA, Edexcel, OCR, Eduqas, CCEA

Learning Objectives

Prerequisites

Materials & Equipment

Lesson 1: Introduction: sequential logic & flip-flops

Duration: 50 minutes

Starter Activity (5 minutes)

Quick Recall

Write down everything you already know about sequential logic & flip-flops. Then check against the key terms: key terms from sequential logic & flip-flops. Use a mini-whiteboard or paper.

Main Content (35 minutes)

Parent/Teacher Guide:
Before lesson: Read the script below. Pre-teach key vocab: key terms from sequential logic & flip-flops.
If stuck: Re-read the revision notes (link above), then break the content into smaller steps.
Extension: See the Stretch & Challenge ideas in Lesson 4.
Teaching Script (35 mins):
Mins 0-5 - Hook: "Today: sequential logic & flip-flops. By the end you will be able to answer exam questions on it unaided. It connects to the rest of Electronics because the ideas here recur across the spec."
Mins 5-20 - Direct Instruction: Work through the core ideas below one at a time; after each, ask your student to explain it back in their own words.
Mins 20-30 - Guided Practice: Model the worked example together, then let your student attempt the first practice question with guidance.
Mins 30-35 - Independent Practice: 2-3 practice questions from Lesson 3 below, with immediate feedback.
First Look

Start with the revision notes summary, then attempt: explain the key ideas of sequential logic & flip-flops

Plenary (5 minutes)

Check Out

Your student states one thing they learned and one question they still have about sequential logic & flip-flops.

Lesson 2: Core Concepts: sequential logic & flip-flops

Duration: 50 minutes

Starter Activity (5 minutes)

Review Previous Lesson

Quick recap: write 3 key points from Lesson 1 on sequential logic & flip-flops. Check them against the notes below.

Main Content (35 minutes)

Key Fact: Sequential logic circuits have memory; their output depends on both current inputs and previous states.
Key Fact: An SR latch (Set-Reset) is the simplest memory element, built from two cross-coupled NAND or NOR gates.
Key Fact: The SR latch using NOR gates: S=1,R=0 sets Q=1; S=0,R=1 resets Q=0; S=0,R=0 holds state; S=1,R=1 is invalid.
Key Fact: A D flip-flop (data) captures the D input value on the clock edge; Q follows D when clocked.
Key Fact: A JK flip-flop generalises the SR latch: J=1,K=0 sets; J=0,K=1 resets; J=0,K=0 holds; J=1,K=1 toggles.
Key Fact: The toggle feature of JK flip-flops (J=1,K=1) makes them ideal for building binary counters.

Practice (10 minutes)

Q: explain the key ideas of sequential logic & flip-flops

Answer:

Plenary (5 minutes)

Explain Back

Your student teaches the key points back to you without looking. Fill any gaps immediately.

Lesson 3: Application: sequential logic & flip-flops

Duration: 50 minutes

Starter Activity (5 minutes)

Quick Recall

Recall the key terms: key terms from sequential logic & flip-flops. Define each in one sentence.

Main Content (35 minutes)

Parent/Teacher Guide: Let your student attempt each question alone first, then compare with the model answer. Award method marks for correct working even if the final answer is wrong.

Work through the practice questions on the revision notes page for this topic.

Plenary (5 minutes)

Error Review

Review any questions answered incorrectly. Identify whether the error was knowledge, method, or reading the question.

Lesson 4: Exam Practice: sequential logic & flip-flops

Duration: 50 minutes

Starter Activity (5 minutes)

Command Words

Review what these command words require: state (one point), describe (say what happens), explain (say why), compare (both sides), evaluate (judgement).

Main Content (35 minutes)

Extended Answer

Extended question: Full-Mark Response Explain the operation of SR, D and JK flip-flops, and describe how JK flip-flops are used to construct a binary counter. <div class="

An SR latch has two inputs: Set (S) and Reset (R). Setting (S=1, R=0) makes Q=1; resetting (S=0, R=1) makes Q=0; S=0, R=0 holds the previous state; S=1, R=1 is invalid because both Q and Q' would be 0. A D flip-flop has a single data input D and a clock. On the active clock edge, Q takes the value of D. This eliminates the SR invalid state since only one input determines the next state. A JK flip-flop has J and K inputs: J=1,K=0 sets; J=0,K=1 resets; J=0,K=0 holds; J=1,K=1 toggles the output. The toggle mode is unique to the JK flip-flop and makes it ideal for counters. A binary counter is built by connecting JK flip-flops with J=K=1 (toggle mode). The first flip-flop toggles on every clock pulse (LSB). Its Q output clocks the next flip-flop, which toggles at half the rate, and so on. This creates a ripple counter that counts in binary from 0 to 2ⁿ−1. For a synchronous counter, all flip-flops share the same clock, and J-K inputs are driven by logic that enables toggling at the correct counts, eliminating ripple delay.

Exam Tips: Draw truth/characteristic tables for flip-flops showing all input combinations and resulting Q. | For counter design, determine the number of flip-flops from n = ⌈log₂(N)⌉ for a modulo-N counter. | Always show the clock signal on timing diagrams and mark the triggering edge. | State the invalid condition for SR latches and explain why JK flip-flops avoid it. | For shift register questions, show data movement step by step with each clock pulse.
Common Errors: ✗ Allowing S=1 and R=1 on an SR latch as a normal operating condition. ✓ S=1,R=1 is the invalid/forbidden state; it violates the bistable condition. Use a JK flip-flop instead, which handles J=1,K=1 as a toggle. ✗ Confusing level-triggered and edge-triggered flip-flop behaviour. ✓ Level-triggered devices respond while the clock is at a level; edge-triggered devices respond only at the instant of the clock transition. ✗ Forgetting to account for propagation delay in ripple counters. ✓ Ripple counters have cumulative delay since each stage waits for the previous one; synchronous counters avoid this with a common clock. ✗ Drawing fewer flip-flops than needed for a counter's modulus. ✓ A modulo-
Stretch & Challenge (Grade 8-9):
  • Synoptic links: explain how sequential logic &amp; flip-flops connects to another Electronics topic you have studied
  • Real-world: research one real-world use or example of sequential logic &amp; flip-flops
  • Critical: "What are the limitations of the models used in sequential logic &amp; flip-flops?"

Plenary (5 minutes)

Assessment Criteria
  • Got it: Confident explanation + correct worked examples
  • Getting there: Main points OK, needs support with detail
  • Not yet: Confused on key concepts - re-run Lesson 2

Homework & Consolidation

Recommended Resources

🎓 Smart Lesson (Guided)