systems architecture
4 detailed 50-minute lessons with teaching scripts, worked examples, parent guides, and assessment criteria.
Lesson Overview
Total Lessons: 4
Tier: Foundation and Higher
Duration: 50 minutes per lesson (200 minutes total)
Exam Boards: AQA, Edexcel, OCR, Eduqas, CCEA
Tier: Foundation and Higher
Duration: 50 minutes per lesson (200 minutes total)
Exam Boards: AQA, Edexcel, OCR, Eduqas, CCEA
Learning Objectives
- Explain the key ideas of systems architecture
- Apply systems architecture to exam-style questions
- Develop independent study skills
- Build cross-topic connections
Prerequisites
- Read the revision notes for systems architecture first (GCSE Revise summary)
- Key vocab to pre-teach: Key Concept, Key Concept, Key Concept
- Basic skills: reading the summary notes and answering the practice questions there
Materials & Equipment
- Exercise book, coloured pens
- Scientific calculator
- Ruler
- Printed revision notes (link below)
- Internet for videos (see Resources)
Lesson 1: Introduction: systems architecture
Duration: 50 minutes
Starter Activity (5 minutes)
Quick Recall
Write down everything you already know about systems architecture. Then check against the key terms: Key Concept, Key Concept, Key Concept. Use a mini-whiteboard or paper.
Main Content (35 minutes)
Parent/Teacher Guide:
Before lesson: Read the script below. Pre-teach key vocab: Key Concept, Key Concept, Key Concept.
If stuck: Re-read the revision notes (link above), then break the content into smaller steps.
Extension: See the Stretch & Challenge ideas in Lesson 4.
Before lesson: Read the script below. Pre-teach key vocab: Key Concept, Key Concept, Key Concept.
If stuck: Re-read the revision notes (link above), then break the content into smaller steps.
Extension: See the Stretch & Challenge ideas in Lesson 4.
Teaching Script (35 mins):
Mins 0-5 - Hook: "Today: systems architecture. By the end you will be able to answer exam questions on it unaided. It connects to the rest of Combined Science (Trilogy) because the ideas here recur across the spec."
Mins 5-20 - Direct Instruction: Work through the core ideas below one at a time; after each, ask your student to explain it back in their own words.
Mins 20-30 - Guided Practice: Model the worked example together, then let your student attempt the first practice question with guidance.
Mins 30-35 - Independent Practice: 2-3 practice questions from Lesson 3 below, with immediate feedback.
Mins 0-5 - Hook: "Today: systems architecture. By the end you will be able to answer exam questions on it unaided. It connects to the rest of Combined Science (Trilogy) because the ideas here recur across the spec."
Mins 5-20 - Direct Instruction: Work through the core ideas below one at a time; after each, ask your student to explain it back in their own words.
Mins 20-30 - Guided Practice: Model the worked example together, then let your student attempt the first practice question with guidance.
Mins 30-35 - Independent Practice: 2-3 practice questions from Lesson 3 below, with immediate feedback.
First Look
Start with the revision notes summary, then attempt: Describe the role of each of the following CPU components: ALU, Control Unit, PC, MAR, MDR, ACC.
Plenary (5 minutes)
Check Out
Your student states one thing they learned and one question they still have about systems architecture.
Lesson 2: Core Concepts: systems architecture
Duration: 50 minutes
Starter Activity (5 minutes)
Review Previous Lesson
Quick recap: write 3 key points from Lesson 1 on systems architecture. Check them against the notes below.
Main Content (35 minutes)
Definition: The CPU (Central Processing Unit) is the brain of the computer. It processes data by executing instructions. The CPU contains the ALU, control unit, clock, and registers, connected by internal buses.
Definition: Registers are small, very fast memory locations inside the CPU. They hold data and instructions currently being processed. Registers are the fastest type of memory in a computer system.
Definition: Buses are parallel wires that connect components of the computer system, allowing data, addresses, and control signals to move between them.
Definition: The fetch-decode-execute cycle (also called the instruction cycle) is the process the CPU follows for every instruction. It fetches the next instruction from memory, decodes it to understand what to do, then executes it.
Key Concept: Clock speed determines how many instruction cycles the CPU can perform per second. A higher clock speed means more instructions can be processed in the same time.
Key Concept: A core is a complete processing unit within the CPU. A multi-core processor has multiple cores that can execute instructions simultaneously.
| Term | Meaning | Example |
|---|---|---|
| PC | Program Counter | Holds the memory address of the NEXT instruction to be fetched |
| MAR | Memory Address Register | Holds the address in memory that is about to be read from or written to |
| MDR | Memory Data Register | Holds the data that has been read from or is about to be written to memory |
| ACC | Accumulator | Holds the results of calculations performed by the ALU |
| CIR | Current Instruction Register | Holds the instruction that is currently being decoded and executed |
| Address Bus | Memory addresses | Unidirectional (CPU → memory) |
| Data Bus | Data and instructions | Bidirectional |
| Control Bus | Control signals (read, write, clock) | Bidirectional |
Practice (10 minutes)
Q: Describe the role of each of the following CPU components: ALU, Control Unit, PC, MAR, MDR, ACC.
Answer: ALU: performs arithmetic and logic operations. Control Unit: coordinates all CPU activities, decodes instructions. PC: holds the memory address of the next instruction to fetch. MAR: holds the memory address to read from or write to. MDR: holds the data being read from or written to memory. ACC: stores the results of ALU calculations.
Plenary (5 minutes)
Explain Back
Your student teaches the key points back to you without looking. Fill any gaps immediately.
Lesson 3: Application: systems architecture
Duration: 50 minutes
Starter Activity (5 minutes)
Quick Recall
Recall the key terms: Key Concept, Key Concept, Key Concept. Define each in one sentence.
Main Content (35 minutes)
Parent/Teacher Guide: Let your student attempt each question alone first, then compare with the model answer. Award method marks for correct working even if the final answer is wrong.
Q1: Describe the role of each of the following CPU components: ALU, Control Unit, PC, MAR, MDR, ACC.
Answer: ALU: performs arithmetic and logic operations. Control Unit: coordinates all CPU activities, decodes instructions. PC: holds the memory address of the next instruction to fetch. MAR: holds the memory address to read from or write to. MDR: holds the data being read from or written to memory. ACC: stores the results of ALU calculations.
Q2: Explain the three stages of the fetch-decode-execute cycle.
Answer: Fetch: the address in the PC is copied to the MAR, the instruction at that address is copied to the MDR, then to the CIR, and the PC is incremented. Decode: the control unit decodes the instruction in the CIR to identify the operation and operands. Execute: the instruction is carried out (e.g. ALU performs calculation) and results are stored in the ACC or written to memory.
Q3: How does increasing the number of cores affect CPU performance? Why doesn't doubling the cores double the speed?
Answer: More cores allow the CPU to process multiple instructions simultaneously (parallel processing). However, doubling cores does not double speed because: not all tasks can be divided into parallel parts, some software is not written to use multiple cores, and cores share some resources (cache, bus bandwidth).
Q4: What is the purpose of cache memory? Why does a larger cache improve performance?
Answer: Cache stores frequently used data and instructions close to the CPU, providing faster access than RAM. A larger cache holds more frequently used data, reducing cache misses (times the CPU must wait for data from slower RAM). Fewer cache misses = less wasted time = better performance.
Q5: State whether each bus is unidirectional or bidirectional: address bus, data bus, control bus.
Answer: Address bus: unidirectional (CPU to memory). Data bus: bidirectional. Control bus: bidirectional.
Plenary (5 minutes)
Error Review
Review any questions answered incorrectly. Identify whether the error was knowledge, method, or reading the question.
Lesson 4: Exam Practice: systems architecture
Duration: 50 minutes
Starter Activity (5 minutes)
Command Words
Review what these command words require: state (one point), describe (say what happens), explain (say why), compare (both sides), evaluate (judgement).
Main Content (35 minutes)
Extended Answer
Extended question: Full-Mark Response Describe the role of the CPU in the Fetch-Decode-Execute cycle, explaining the purpose of the Program Counter, Memory Address Register, and Accumulator. [5 marks] <div class="
The CPU continuously performs the Fetch-Decode-Execute cycle: FETCH: The Program Counter (PC) holds the address of the next instruction. This address is copied to the Memory Address Register (MAR). The instruction at that address is fetched from RAM and stored in the Memory Data Register (MDR). The PC is then incremented to point to the next instruction. DECODE: The Control Unit (CU) decodes the fetched instruction to determine what operation to perform and what data is needed. EXECUTE: The Arithmetic Logic Unit (ALU) performs any calculations or logic operations. The result is stored in the Accumulator (a special register that holds the results of arithmetic/logic operations). If needed, the result may be stored back in RAM. The cycle then repeats from FETCH.
Exam Tips: Know all CPU components and registers with their full names and functions | Be able to describe the fetch-decode-execute cycle step by step | Remember: PC = next instruction address, CIR = current instruction, ACC = calculation result | For performance questions, discuss clock speed, cores, AND cache | Never say "more cores = double the speed" - explain parallel processing carefully | Know the direction of each bus: address = one way, data and control = both ways
Common Errors: ✗ Confusing the ALU and the CU within the CPU ✓ The ALU (Arithmetic Logic Unit) performs calculations and logical comparisons. The CU (Control Unit) manages and coordinates all CPU activities, decoding instructions and sending control signals. ✗ Thinking more cores always means faster performance for all programs ✓ More cores improve performance for programs designed to split work across cores (parallel processing). Single-threaded programs only use one core, so extra cores provide no benefit. ✗ Believing cache memory is the same as RAM ✓ Cache is much smaller, faster, and more expensive than RAM. It sits between the CPU and RAM, storing frequently used instructions/data to reduce access tim
Stretch & Challenge (Grade 8-9):
- Synoptic links: explain how systems architecture connects to another Combined Science (Trilogy) topic you have studied
- Real-world: research one real-world use or example of systems architecture
- Critical: "What are the limitations of the models used in systems architecture?"
Plenary (5 minutes)
Assessment Criteria
- Got it: Confident explanation + correct worked examples
- Getting there: Main points OK, needs support with detail
- Not yet: Confused on key concepts - re-run Lesson 2
Homework & Consolidation
- Consolidation: Re-answer any Lesson 3 practice questions answered incorrectly (20 mins)
- Retrieval: Write flashcards for the key terms: Key Concept, Key Concept, Key Concept (10 mins)
- Exam practice: One past-paper question on systems architecture from the board websites (15 mins)
- Extension: Explain systems architecture to someone else in your own words (10 mins)